/ The Ultimate Amiga 500 Talk \

Bernhard R. Fischer

2048R/5C5FFD47, bf@abenteuerland.at
Eventphone GSM: 9290

#32C3, Hamburg, 2015

Amiga History

1985: Amiga 1000
1987: Amiga 500 & Amiga 2000
1990: Amiga 3000
1992: Amiga 1200 & Amiga 4000
...1992: Wolfenstein 3D
...1993: Doom
1994: Bankruptcy of Commodore Inc.
...
2000: AmigaOne, PPC-based, AmigaOS 4,
Hyperion Entertainment

Amiga Models

Competitors

Atari ST, CPU 68k family, 1985
Acorn Archimedes, CPU ARM2, 1987
Apple Macintosh series, CPU 68k, 1985
Intel-based models, CPU 80386, 1987
(VGA 1987, OS/2 1987, AIX 1986,
Windows 3.0 1990, X11 1987,
Linux 1991)

OS Versions

Version 1.0 - 1.3, original versions
Version 2.0, ~1990, new chipsets
Version 3.0, 1992 A1200 & A4000
Version 4.x, 1994, non-Commodore,
PPC, chipset-independent

Books

Core Components

32 bit Motorola 68000 CPU
512k RAM, expandable to 8 MB
256k/512k ROM
pre-emptive real-time multi-tasking
GUI-based OS
serial & parallel port,
mouse/joystick/ligh pen/... ports
built-in 3 1/2" disk drive
expansion slot(s) for additional hardware
analog and digital video output
stereo audio output

Amiga 500 Rear View

Technical Specs

7.09379 MHz CPU Clock (7.15909 Mhz on NTSC)
Custom chips Agnus, Paula, and Denise
Video beam synchronized coprocessor: COPPER
Coprocessor for image manipulation: BLITTER
further DMA channels for
audio, bitplanes, floppy disks, sprites...
Pixel resolution 640x512 and 12 bit color depth
4 audio channels
All sub-systems are interrupt controlled

Programming Languages

C
Assembler
AmigaBASIC
ARexx, versions >= 2.0

68000 CPU

released 1979
16-bit OP codes, orthogonal instruction set
12 addressing modes
(nearly) 32 bit ALU
8 32-bit data registers
8 32-bit address registers (incl. SP)
system status register
256 interrupts
user and supervisor mode
external 16 bit databus
external 24 bit address bus (16 MByte)

68000 Assembler

   move.l   a0,cl_clist
   moveq    #15,d0
mn_col1   moveq    #15,d1
   sub.w    d0,d1
   move.w    d1,d2
   add.w    d1,d1
   add.w    #$2d,d1
   lsl.w    #8,d1
   addq.b   #1,d1
   move.w    d1,(a0)+
   move.w   #$ff00,(a0)+
   move.w    #COLOR01,(a0)+
   lsl.w    #4,d2
   or.w    #$0f00,d2
   move.w    d2,(a0)+
   move.w   #BPLCON1,(a0)+
   move.w   #0,(a0)+
   dbf    d0,mn_col1
   moveq   #15,d0

68xxx followup models

68010: virtual memory support
68020: full 32 bit ALU, external 32 bit bus,
MMU support, instruction cache
68030: built-in MMU
68040: built-in FPU
...

A500 Mainboard

A500 2 MB (1.8MB) Slow RAM extension

A2000 Mainboard

A2000 SCSI Controller

Hardware Block Diagram

Functional Block Diagram

Memory Map

$000000 - $07ffff 512 kB chip RAM
$080000 - $0fffff 512 kB extended chip RAM ("Big/Fat Agnus")
$100000 - $1fffff 1 MB extended chip RAM ("ECS Agnus")
$200000 - $9fffff 8 MB AUTOCONFIG space ("fast RAM")
$a00000 - $beffff reserved
$bfd000 - $bfdf00 8520-A
$bfe001 - $bfef01 8520-B
$c00000 - $d7ffff 1.5 MB internal expansion "pseudo fast RAM"
$d80000 - $dbffff 256k internal explansion "pseudo fast RAM"
$dc0000 - $dcffff real time clock
$dff000 - $dfffff custom chip registers
$e00000 - $e7ffff reserved
$e80000 - $efffff temp. AUTOCONFIG space
$f00000 - $fbffff 256k ROM (since OS version >= 2.0)
$fc0000 - $ffffff 256k ROM

Custom Chips

~200 custom chip registers (CCR)
starting at $DFF000
interrupt and bus control
bitplane, audio, and disk DMA
BLITTER
COPPER

Bitplane DMA/Video Hardware

320x256, 640x256, non-interlaced
320x512, 640x512, interlaced
bitplane-based color selection (next slide)
up to 6 bitplanes
32 color registers, 4096 colors
(3 x 4 bits RGB)
special modes
- dual playfield mode (see next slide)
- HAM -- Hold And Modify, 4096 simultaneous colors
- Halfbrite -- 6th bitplane selects brightness

Bitplanes

Dual Playfield Mode

Sprites

8 sprites (2 bitplanes each)
...or 4 sprites in attached mode
(4 bitplanes each)
reusable DMA channels (= more than 8 sprites)
hardware-based collision detection
(+ playfield collision)

Display Generation

BPLs are separately memory addressed (in CCRs)
and pixel positioned (delayed)
Sprites are memory addressed (in CCRs)
and pixel positioned

Video hardware (Denise)
...reads bits
...determines priority
...chooses color (from CCRs)
...generates beam color
...detects collisions

COPPER

video beam synchronized coprocessor
3 commands: WAIT, MOVE, SKIP
used to modify custom chip registers
could even modify its own registers
bus priority over BLITTER and the CPU

BLITTER

(image) data copy and modification engine
(16-bit word-based)
4 DMA channels: 3 sources (A, B, C),
1 destination (D)
256 boolean functions to combine A, B, and C,
such as (A/BC) + (A/B/C) + ...
bit shifting and masking of data
descending and ascending operation
area filling
(textured) line drawing

Bus Timing

Audio Hardware

4 independent 8-bit audio channels
max. sampling rate ~28900/s,
i.e. 14.5 kHz audio (with DMA)
support for additional frequency and/or
amplitude modulation
interrupt driven reload of sample data
programmed by CCRs, data pointers,
volume and sampling rate

Interrupt Summary

vertical blank interrupt (~5600 cycles)
COPPER interrupt (specific beam position)
audio interrupt (block done)
BLITTER finished
disk interrupt: disk sync or DMA finished
CIAs (e.g. serial ports)
external interrupts (expansion boards)

Floppy Disks

flexible disk controller
up to 4 drives, 3 1/2"
simultanous access to several drives
standard format: 80 tracks, 2 sides,
11 sectors = 880 kByte
could read other formats as well
(e.g. IBM PC 80 * 2 * 9 = 720 kByte

OFS: 488 bytes/sector
FFS: 512 bytes/sector

__/ The Ultimate Amiga 500 Talk \__